Technical presentation - 30 minutes (including q&a)
Trusted Firmware-A provides an open-source reference implementation of the secure software for Armv8-A and Armv9-A. It provides SoC developers and OEMs with a reference trusted code base complying with the relevant Arm specifications for A-class processors. The TF-A code is the preferred implementation of Arm A-class CPU specifications, allowing quick and easy porting to modern chips and platforms. This forms the foundations of a Trusted Execution Environment (TEE) on application processors TF-A LTS was officially proposed in July 2022 by 2 partners in a TF-A Technical Forum presentation. This proposal was accepted by the trustedfirmware.org TSC and quickly gained steam with some of the Arm partners who needed long term software support based on the product life cycle in Client devices, which has recently been extended to 7 years. The first TF-A LTS release made in February 2023 was based on the TF-A v2.8 release, with the alignment to make a TF-A LTS major release branch based on the second TF-A release in a calendar year. The presentation predominantly covers the evolution of the TF-A LTS in terms of the LTS branches, process, release procedures and automation during the course of the first 2 major LTS releases in 2023 and 2024. It also covers recommended use and some of the challenges faced in maintaining the LTS branches. The intent of the presentation also includes creating a broader awareness of the existence of TF-A LTS to the Arm ecosystem and how it benefits the partners in longer term. This is also a call for interested partners to join and support the TF-A LTS maintenance efforts and add value to the Arm ecosystem by contributing to the joint effort.
I am a Principal Software Engineer working with Arm for the past 11+ years leading and line managing the TF-A sub-team in Austin. I am involved with the Trusted Firmware project from 2019 and been leading the TF-A LTS maintainership efforts for Arm along with other maintainers from partners like NVIDIA, Google, ST Micro etc. I am also leading the security and errata mitigations of various CPUs within the TF-A project. Prior to the TF-A project, I was involved with leading, architecting and implementing a customizable architectural verification tool for the Arm CPU memory subsystem. Before Arm, I worked with Texas Instruments leading the Microprocessor subsystem RTL/gate level verification and Silicon validation for various generations of OMAP SoCs, unit and top-level RTL verification of L1 and L2 memory subsystems etc.